Simulating mixed language HDL using VCS

I needed to port some modelsim do files to this new simulator so I found out that the documentation available is not as friendly as I would like. Finally got to get the simulation working and I want to archive it somewhere it can help me or someone else in the future.

This little tutorial is supposed to be dynamically updated when I feel that more info is needed or find errors in it.

VCS is a simulator from Synopsys which is known to be far superior to Xilinx ISim. It support multiple languajes such as the most popular Verilog, VHDL, SystemVerilog.

General workflow
The general workflow when simulating with VCS consist of the following steps.

• Compile/Analize
• Elaborate/Build
• Simulate

First, you need to compile each and every HDL files you have in your design including the testbench. This is done with different command lines such as

• vhdlan: The compiler for VHDL files
• vlogan: The compiler for Verilog and SystemVerilog files.

Both commands accept the flag -f filelist where "filelist" is a list of files to be compiled. This help a lot to simplify and structure the compilation scripts.

VHDL Compilation/Analysis

VHDL uses libraries to organize code, getting vhdlan to compile them is not straight forward since vcs needs to map them to some directory and then link them.

To achieve this you must create a directory with the name of each the library in your pwd to be able to map the libraries to a physical directory. The way to tell vcs how to map each library to the directories a special file is needed: .synopsys_vss.setup. This file can be on your VCS instalation path, in your $HOME or in your pwd, vhdlan will look for the file in this particular order.

The syntax of this file is somehow easy, you first need to map the WORK library to a name, which then must be maped to a physical directory, after that, each library must be mapped to a physical directory on each line.

In the following example, there are two libraries, MY_LIB with some modules of my own and UTIL_LIB which have util modules designed over the time.

WORK > DEFAULT
DEFAULT : ./work
MY_LIB : ./MY_LIB
UTIL_LIB : ./UTIL_LIB

This is a simple command line used to compile VHDL files with libraries

vhdlan -work <library_dir> -f <filename_of_file_list>

Verilog Compilation/Analysis

Verilog doesn't uses libraries so there is not need to do tricks with the libraries. Still it's useful to know some tricks about this complier.

vlogan have some useful flags that helps to structure the code and maintain isolated the simulation environment to the development one.

• +incdir+: Specify the path where vlogan will look for the files to compile.
• +define+: Define a text macro at compile time.
• +v2k: Enables the use of Verilog Standard 2001
• -svlog or -sverilog: Enables the analysis of SystemVerilog code.

This is the simple command line used to compile Verilog files using 2001 standard and a SystemVerilog test bench.

vlogan +v2k +incdir -f <filename_of_file_list>
vlogan +v2k -sverilog +incdir -f <filename_of_file_list>

 vlogan write it's output in a directory AN.DB which can be deleted in a cleanup process to keep workspace clean.

Elaboration/Build

Once every file needed in a design is compiled, now it is time to elaborate the executable binary. The command to elaborate is vcs which take as parameter the top module to be simulated, usually the top module of the testbench.

The command to elaborate is:

vcs -debug_all glbl

where the flag -debug_all tell the tool to enable the simulation GUI and the necessary debug information to add breakpoints and line stepping. The glbl argument is needed to use Xilinx components.

Simulation

The elaboration command generates an executable file with the name of simv which must be executed to start the simulation. The default behavior of this executable is to run and output messages from the test bench to stdout. Normally what is needed is to get a GUI where to see the waves and analyze the signal values at each time, this is done with the -gui parameter.

The command to execute the simulation with a GUI is:

./simv -gui

Conclusion

This is the basic workflow needed to simulate a design in VCS, each of the tools have a lot more parameters that can be used to get specialized behavior when needed. All of them come with the documentation of the tools through the manuals or the -h parameter.

[1] VCS and coverage by Aviral Mittal
Update: This is the original link to the article I found useful
Update: Fix some escaped out <info> comments.

Split large LaTeX files

When your paper/report is getting too large it becomes a little complicated/frustrated to maintain it in one big file.

It's possible to split a big .tex file and setup a hierarchical file tree with a small portion of the text on each file.This is achieved using the \include directives.

There are three main LaTeX commands that manage multiple input files.

• \includeonly which specifies a list of files that will be included by the \include command. If this command exists and file in \include is not listed here, it will not be included
• \include as it's name says, it include a file in a new page. Used with \includeonly, it can include files selectively. Note: This command can't be nested
• It's equivalent to \clearpage \input{file} \clearpage
• \input This is the most simple include scheme and it is equivalent tot a plain C's #include

So your big file 

\section{foo}
% lot of text, figures and equations
\section{bar}
%lot of text and subsections>

can be simplified as

\include{foo}
\include{bar} 

where there is a foo.tex an bar.tex sub-files containing the section text.

If you want to get another layer of simplifications, it's possible to just use \input in the sub-files.

[1] http://www.kfunigraz.ac.at/~binder/texhelp/ltx-165.html